1. Field of the Invention
The present invention relates to a semiconductor device and a cell.
2. Description of the Background Art
Along with recent advancements in the miniaturization techniques, the degree of integration of integrated circuits (semiconductor devices) is increasing. FIG. 12 is a partially cutaway plan view showing a conventional semiconductor device 1200 as disclosed in Japanese Laid-Open Patent Publication No. 2002-261245. The semiconductor device 1200 includes a plurality of cells 1201, a power supply line 1203b, a ground line 1203a, a strap power supply line 1202b and a strap ground line 1202a. Each cell 1201, being a circuit component forming a circuit together with other cells, may be, for example, a basic cell that implements an AND gate or a NAND gate, or a cell including a plurality of gates such as AND gates. An intended integrated circuit can be realized by combining a plurality of such cells together.
The power supply line 1203b is electrically connected to a power supply pad (not shown) provided in the I/O region around the semiconductor device 1200. The ground line 1203a is electrically connected to a ground pad (not shown) provided in the I/O region around the semiconductor device 1200. The power supply line 1203b and the ground line 1203a extend parallel to each other. Although not shown in FIG. 12, the supply line 1203b and the ground line 1203a alternate with each other. Moreover, the power supply line 1203b and the ground line 1203a are formed in the same wiring layer.
The strap power supply line 1202b extending perpendicular to the power supply line 1203b is formed in the same wiring layer as the power supply line 1203b, and is electrically connected to the power supply line 1203b. The strap ground line 1202a extending perpendicular to the ground line 1203a is electrically connected to the ground line 1203a. The strap power supply line 1202b and the strap ground line 1202a alternate with each other with an interval therebetween that is dictated by the height of the cell 1201. The cells 1201 in each horizontal row 1201X as shown in FIG. 12 are supplied with a power supply voltage from the power supply line 1203b via the strap power supply line 1202b and a ground voltage from the strap ground line 1202a via the strap ground line 1202a. The input terminal of each cell 1201 is connected to the output terminal of another cell via signal lines 1206, 1207, etc.
If the degree of circuit integration is increased without changing the power supply voltage, the power consumption of the circuit increases. In view of this, the power supply voltage is conventionally decreased as the degree of circuit integration is increased. As the power supply voltage is decreased, the absolute value of the threshold voltage of each transistor formed in a cell is also decreased. The lower the threshold voltage is, the more likely it is that a transistor may malfunction because of voltage fluctuations due to noise. Therefore, a stable power supply voltage with no variations should be supplied to the cells.
In order to suppress variations among power supply voltages to the cells, the line resistance should be suppressed. The line resistance can be suppressed by increasing the number of power supply lines connected in parallel to one another to reduce the resistance of each power supply line, or by increasing the width of each power supply line.
However, if the number of power supply lines or the width thereof is increased, the area of the region in which the power supply line or the ground line is formed increases, thereby increasing the overall size of the semiconductor device. A larger size of a semiconductor device means a smaller number of semiconductor chips per wafer and a lower production yield, which both increase the production cost.
If the width of the power supply line is increased, the space in which signal lines can be provided is decreased, and the signal lines connecting cells together may need to be routed around, making it more difficult to meet the signal timing constraints. If there is a signal line that does not meet the timing constraints, it is necessary to reexamine the HDL design (design using a hardware description language) or to modify the layout design until the timing constraints are met, thereby increasing the number of design steps and the overall design period. Thus, there should be a sufficient space for placing signal lines without much routing around.